This invention relates generally to methods of manufacturing multilayer circuit boards and multichip modules, referred to collectively herein as circuits. More particularly, this invention relates to new and improved methods of manufacturing multilayer circuits wherein interconnections between multichip module assemblies (circuit assemblies) is accomplished in a single lamination step utilizing a fluoropolymer composite material and diffusible conductive material (e.g. a noble metal).
The need for and desirability of substrates for MCM's is well known in the electronic industry. The need for increased density in I/C packaging, increased interconnection capacity, and improved interconnection performance is well known among those involved in VLSI packaging and elsewhere in the electronics industry.
A multichip module can be viewed as a packaging technique in which several I/C chips, which may include complex microprocessor chips, memory chips, etc., are interconnected by a high density substrate. Although substrates for MCMs have been known in general for several years, these known prior art substrates for MCMs typically use thin film polyimide based material systems, and those systems have known deficiencies. Polyimide dielectric materials suffer from poor thermo-mechanical reliability and stability and electrical performance limitations. The polyimide materials usually are thermosetting, and have high elastic modulus, and there is a significant mismatch, i.e., difference, between the coefficient of thermal expansion (CTE) of the polyimide and the copper-conductors and/or other elements of the circuit structures. That all results in high stresses in the polyimide material and in surrounding materials and interfaces during thermal excursions in either or both the manufacturing process for or during use of the MCM substrate. Those stresses can lead to dimensional instabilities, cracking, delamination and other thermomechanically related problems. Also, the chemical bond between the polyimide and the copper conductors may be weak and is usually sensitive to the presence of water, thus leading to poor reliability of the copper-polyimide interface.
In some manufacturing processes for polyimide-based substrates for MCMs, a liquid form polyimide precursor is applied and then cured; in other processes, a sheet form polyimide prepreg is used. In either case, it is difficult to keep water out of the MCM substrate structure made with polyimides. Water is often generated during the polyimide cure, and the polyimide equilibrium water absorption is substantial, often in excess of 1%, and the rate of water uptake can be high. Also, water diffusion rates in polyimides are often high, so any water in a polyimide MCM substrate structure can diffuse quickly to the polyimide-conductor interface to corrode or otherwise degrade the interface. To combat this interface problem, a layer of metal, usually chromium is used as a barrier layer between the polyimide and the copper conductors. While this use of a barrier layer can be successful, it adds significant and expensive processing steps and costs to the manufacture of the MCM substrate structure.
Another point to note about polyimide based substrates for MCMs is that they are thin film structures. The layers of polyimide are typically in the range of 5 to 12 microns in thickness, with conductor line thickness in the range of 2 to 7 microns. Those relatively thin conductor lines mean relatively high resistance and relatively high loss; and both the nature of the polyimide material, per se, and the relatively thin layers used, result in poor electrical insulation characteristics.
Multilayer circuits are also well known and comprise a plurality of stacked substrate/circuit trace assemblies with interconnections between selected locations on the spaced circuit traces. Conventional manufacturing techniques for multilayer circuits generally do not yield multiple levels of interconnect, i.e. easy interconnection from one layer to any other layer without significant loss of density and/or major increases in processing costs. This limits the circuit density and the number of substrates. When multiple interconnect levels are required, step intensive sequential process techniques are usually utilized with much reduced yields.
U.S. Pat. No. 4,788,766 attempts to overcome these problems. This prior patent discloses a method wherein a multilayer assembly is made up of a number of individual circuit boards and each board has a substrate on which a first conductive layer is formed on one surface while a second conductive layer is formed on the opposite surface. The substrate is a dielectric material which insulates the conductive layers. Via holes are formed through the first conductive layer, the substrate and the second conductive layer at various locations. An outer conductive material, such as copper, is applied over the first and second conductive layers and onto the side walls of the holes. A conductive bonding material is then deposited onto the outer conductive material in the area around the holes. Once the individual boards have been fabricated, they are stacked in a predetermined order and orientation with a suitable low temperature dielectric bonding ply (meaning that the bonding ply has a lower softening temperature than the circuit substrate material) positioned between each pair of layers. The dielectric bonding ply requires registered apertures therethrough which correspond to areas where the conductive layer of one substrate is to make an electrically conductive connection with the conductive layer of an adjacent substrate. Thus, the dielectric bonding ply integrally bonds adjacent boards together while providing electrical isolation and/or electrical connections between conductive layers of different boards. The assembly of the boards is then subjected to a cycle of heat and pressure to effect a bond between the various board layers.
While the method of U.S. Pat. No. 4,788,766 overcomes some of the problems in the prior art, this prior method has certain disadvantages including the requirement for a substrate which has a melting temperature above the melting temperature of the bonding ply. In other words, the prior patent necessitates the use of a low temperature bond ply which limits the thermal rating of the multi-layer circuit. In addition, this prior method necessitates registered apertures in the bonding ply (leading to alignment problems) and is limited to multilayer circuits having plated through holes.
U.S. Pat. No. 5,046,238 attempts to overcome these problems. This prior patent discloses a method wherein a plurality of circuit layers comprised of a dielectric substrate having a circuit formed thereon are stacked, one on top of the other. The dielectric substrate is composed of a polymeric material capable of undergoing fusion bonding such as a fluoropolymeric based substrate. Fusible conductive bonding material (e.g., solder) is applied on selected exposed circuit traces (prior to the stacking step) whereupon the entire stack is subjected to lamination under heat and pressure to simultaneously fuse all of the substrate and conductive layers together to form an integral multilayer circuit having solid conductive interconnects.
In the first embodiment of U.S. Pat. No. 5,046,238, the discrete circuit layers are each prepared by (1) forming traces and pads on a removable mandrel; (2) laminating a layer of dielectric to the circuit and mandrel; (3) forming an access opening at selected locations through the dielectric layer (using laser, plasma, ion etch or mechanical drilling techniques) to expose selected circuit locations; (4) forming conductive posts in the access openings to a level below the top of the access openings; and (5) providing a fusible conductive material in the access opening. Thereafter, a stack-up is made of a plurality of these discrete circuit layers so that the exposed fusible conductive material contacts selected locations on an adjacent circuit. This stack-up is then subjected to heat and pressure to simultaneously fuse both the several layers of dielectric substrate and fusible conductive material to provide a cohesive fused multilayer circuit board.
In the second embodiment of U.S. Pat. No. 5,046,238, at least one discrete circuit board is made using any suitable technique to define a fusible dielectric substrate having a circuit pattern thereon. Next, a layer of fusible dielectric material having openings through selected locations is placed on the circuit board so that selected locations on the circuit pattern are exposed. Thereafter, a plug of fusible conductive material (e.g., solder) is placed in the openings (using manual, mechanical or like techniques). Next, a second circuit board is stacked on the first board so that the plugs of fusible conductive material align with and contact selected locations on the circuit pattern of the second circuit board. This stack-up is then subjected to heat and pressure to simultaneously fuse both the layers of fusible dielectric and the fusible conductive material to provide a cohesive fused multilayer circuit board.
While the method of U.S. Pat. No. 5,046,238 overcomes some of the problems in the prior art, this prior art method has certain disadvantages including problems commonly encountered with spreading of the solder mass during lamination, and evolution of the flux medium necessary to deoxidize the solder. Further, spreading of the solder mass is dependent on the low viscosity of the solder, the amount of solder and the proximity of other circuit features. Also, it is difficult to evolve all of the flux compound from the internal layers of the printed circuit board thereby presenting a potential long-term reliability problem from residual organics. With continued microminiaturization of circuit features, it was desired to produce circuit boards with feature sizes smaller than that possible using solder.
Temperatures and pressures used for practical solid state bonding processes are typically well in excess of 300.degree. C. and 1000 psi. Therefore, it is necessary for any dielectric material used to be stable at temperatures above 300.degree. C. It will be appreciated that thermoplastic materials are generally not useful for fabricating very dense circuits with these harsh bonding conditions.
Fluoropolymers dielectric materials are often used for high frequency applications (&gt;1 GHz) due to their low loss and tight dielectric constant control. Fluoropolymers such as polytetrafluoroethylene (PTFE), a copolymer of tetrafluorethylene and perfluoroalkyl vinyl ether (PFA) and a copolymer of hexafluoropropylene and tetrafluoroethylene (FEP) are also excellent circuit substrates due to their good thermal stability up to 400.degree. C. and their good self-adhesion characteristics above their melt point. However, these materials generally have poor creep characteristics and yield poor dimensional stability when circuitized.
To register dense circuit features (traces &lt;150 um and vias &lt;200 um), it is essential that the dielectric material be dimensionally stable. This requires the tailoring of x-y thermal expansion to closely match the metallurgy (in most cases copper) of the circuit features. This must be accomplished without jeopardizing dielectric self-adhesion characteristics, adhesion to conductors or producing unacceptably high porosity.
Thermal compression bonding processes can be practiced at relatively low temperatures and moderate pressures as described in U.S. Pat. No. 3,923,231. However, the time required for bonding is extremely long (22-30 days) so these processes are generally not practical for printed circuit board or multichip module applications. To yield practical bonding times (&lt;5 hour soak times), it is necessary to use relatively high temperatures (&gt;300.degree. C.) and pressures (&gt;1000 psi). U.S. Pat. No. 4,874,721 describes a gold bonding process with pressures of about 2 kg/mm 2 (2800 psi) and 400.degree. C. in 1 hour.
With fluoropolymers, these high temperatures and pressures can produce flow which distorts circuits and produces severe misregistration of individual circuit layers. This problem increases greatly as the density of circuit features increases.